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Apple

IP Timing lead

IP Timing lead

Israel

08.09.2021
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Engineering Program Manager - Wireless technology group

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AppleIP Timing leadIsrael
Details

Summary

Posted:
Role Number:200236952
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an exceptionally talented IP timing lead. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. This role is for a IP timing lead who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of pre-silicon development from definition to high quality tape-out.

Key Qualifications

  • 7+ years of work experience in the timing/STA domain.
  • Thorough knowledge of the ASIC design timing closure flow and methodology.
  • Experience in writing ASIC Timing constraints and Timing closure
  • Expertise in STA tools (Primetime) and flow
  • Knowledge of timing corners/modes, process variations and signal integrity related issues
  • Hands on experience in Timing/SDC constraints generation and management
  • Proficient in scripting languages (Tcl and Perl)
  • Familiarity with synthesis, DFT and backend related methodology and tools.
  • Strong communication skills are a must, as the candidate will interface with a lot of different groups within the company
  • Ability to work well in a team and be productive under tight schedules

Description

Development, ownership of IP level timing constraints both for regular and custom requirements from synthesis to sign-off to achieve sign-off quality timing convergence. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical Design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.

Education & Experience

B.Sc / M.Sc in Electrical Engineering or Computer Engineering from leading universities

Additional Requirements

  • diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other legally protected characteristics. If you’d like more information about your EEO rights as an applicant, please click here. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants. For more information, please click here.
  • Apple participates in the E-Verify program in certain locations as required by law. Learn more.
  • Apple's committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities. Learn more.
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