Intel Senior DFT Engineer 

India, Karnataka, Bengaluru 

610182646

The Graphics hardware IP team , within the CGAI Client Compute Group and AI, is responsible for design and development of Graphics, Media and Display IPs as well as discrete Graphics SoCs GPUs, targeting both Client Device and Datacenter markets. The XSE organization is at the center of Intel's push into the discrete Graphics SoCs ARC GPUs market segment targeting next-generation applications such as High-performance computing, Deep learning / training, Cloud Graphics, Media analytics, High-end gaming.

• Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs.
• Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
• Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure highquality integration of the GPU block.

Qualifications

• You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through relevant schoolwork, internships, jobs and/or research experience.
• Minimum skills and Experience:
  • Bachelors in Electrical/Computer Engineering or related field with 7+ years of academic or industry experience. Or a Masters in the same fields with 5+ Years of academic or industry experience.
  • Your experience should be in the following
    • At least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST)
    • SoC IP DFT design integration or verification
    • EDA tools such as ATPG tools, Mentor Tessent shell, VCS simulation and/or debug tools.
    • Silicon enabling debug or test pattern development experience
• Preferred Skills and Experience
  • At least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST
  • EDA tools such as ATPG tools, Mentor Tessent shell, Synopsis VCS simulation and/or debug tools
  • Structural design flows, including timing, routing, placement or clocking analysis
  • SOC architecture, RTL coding and post silicon debug

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits