Samsung DTCO PPA Architect 

France, Auvergne-Rhône-Alpes 

763649517

Role and Responsibilities

IP (FIP)-Development to unlock new technology potential, which is key towards our business success.

• You will take part in general DTCO activity from early TD up to tape-out and revision.
• You are passionate about leading Foundation IP (FIP) Architecture exploration for new technology. This includes coordinating with the global FIP design team (both in-house and Foundry).
• You are a domain expert in one or more technical areas, such as Advanced Methodology development, ranging from Physical Design (P&R),transistor-level/circuitLayout, Signoff, Electrical/Physical Verification up to DFM. You will help our team coordinate with global designmethodology teamsand will often directly drive global R&D teams from various EDA vendors.
• You have a curious mindset that thrives on navigating the unknown through innovation and continuous learning. Your strong voice will influence our current and future plans strategy.
• You enjoy identifying and distilling complex problems or situations by seeking the root causes and engaging others to brainstorm possible outcomes.
• You are an innovator. You thrive on driving future-oriented changes and generating creative perspectives and solutions. You bring fresh ideas to challenge past practices, approaches, and old ways of thinking to introduce new innovation opportunities.
• You are skilled at driving cross-company collaboration with a global perspective by creating synergetic ways of working using effective communications and proactive partnership. You enjoy helping our team collaborate with internal and external partners to drive technology enablement, while harnessing our diversity as a strength to achieve business results.

Skills and Qualifications

• 6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years of experience with a Master’s Degree, or 2+ years of experience with a PhD
• Technology Enablement (TE) and DTCO experience at advanced technology nodes (below 5nm). The activity includes technology, logic and memory cell architecture exploration, and interconnect option exploration. Multiple-Foundry experience is a big plus.
• Foundation IP (both Library Cell and SRAM Memory) design and architecture experience up to MTO and post-Silicon activity.

Pay Transparency

At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,557.00 and $305,414.00. Your actual base pay will depend on variables that may include youreducation skills,qualifications, experience, and work location.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.